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Single-Chip, Multiband 3G Femtocell Transceiver ADF4602
FEATURES
Single-chip multiband 3G transceiver 3GPP 25.104 release 6 WCDMA/HSPA compatible UMTS band coverage Local area Class BS in Band 1 to Band 6 and Band 8 to Band 10 Direct conversion transmitter and receiver Minimal external components Integrated multiband multimode monitoring No Tx SAW or Rx interstage SAW filters Integrated power management (3.1 V to 3.6 V supply) Integrated synthesizers including PLL loop filters Integrated PA bias control DACs/GPOs WCDMA and GSM receive baseband filter options Easy to use with minimal calibration Automatic Rx DC offset control Simple gain, frequency, mode programming Low supply current 50 mA typical Rx current 50 mA to 100 mA Tx current (varies with output power) 6 mm x 6 mm 40-pin LFCSP package
FUNCTIONAL BLOCK DIAGRAM
GPO[4:1] GPO 1 TO 4 DAC1 DAC2
DAC1
DAC2
ADF4602
Tx_PWR_CONTROL TXBBIB TXBBI
TXLBRF Tx_PWR_ CONTROL TXHBRF Tx_PWR_ CONTROL LO GENERATOR Tx PLL LOOP FILTER FRAC N SYNTHESIZER VSUP7 TXBBQ TXBBQB Tx_PWR_CONTROL
Rx PLL LO GENERATOR LOOP FILTER FRAC N SYNTHESIZER
VSUP6
Rx_LO_LB SELECTABLE BANDWIDTH BASEBAND FILTERS RXHB1RF I CHANNEL RXBBI RXBBIB DC OFFSET CORRECTION RXBBQ Q CHANNEL Rx_LO_LB REFIN 26MHz 19.2MHz SERIAL INTERFACE VDD VSUP8 RXBBQB DC OFFSET CORRECTION
APPLICATIONS
3G home basestations (femtocells) 3G repeaters
RXHB2RF
RXLBRF
LDO1 LDO2 LDO3 LDO4 LDO5
VINT REFCLK
SEN SCLK SDATA
VSUP1
VSUP2
VSUP3
VSUP4
VSUP5
CHIPCLK
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
07092-001
ADF4602 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 Timing Characteristics..................................................................... 8 Absolute Maximum Ratings............................................................ 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 12 Theory of Operation ...................................................................... 17 Transmitter Description ............................................................ 17 DACs ............................................................................................ 18 General Purpose Outputs .......................................................... 18 Receiver Description .................................................................. 18 Power Management ................................................................... 21 Frequency Synthesis ................................................................... 22 Serial Port Interface (SPI) .............................................................. 23 Operation and Timing ............................................................... 23 Registers ........................................................................................... 24 Register Map ............................................................................... 24 Register Description .................................................................. 25 Software Initialization Procedure ................................................. 29 Initialization Sequence .............................................................. 29 Applications Information .............................................................. 31 Interfacing the ADF4602 to the AD9863 ................................ 31 Outline Dimensions ....................................................................... 33 Ordering Guide .......................................................................... 33
REVISION HISTORY
10/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 36
ADF4602 GENERAL DESCRIPTION
The ADF4602 is a 3G transceiver integrated circuit (IC) offering unparalleled integration and feature set. The IC is ideally suited to high performance 3G femtocells providing cellular fixed mobile converged (FMC) services. With only a handful of external components, a full multiband transceiver is implemented. UMTS Band 1 through Band 6 and Band 8 through Band 10 are supported in a single device. The receiver is based on a direct conversion architecture. This architecture is the ideal choice for highly integrated wideband CDMA (WCDMA) receivers, reducing the bill of materials by fully integrating all interstage filtering. The front end includes three high performance, single-ended low noise amplifiers (LNAs), allowing the device to support tri-band applications. The single-ended input structure eases interface and reduces the matching components required for small footprint singleended duplexers. The excellent device linearity achieves good performance with a large range of SAW and ceramic filter duplexers. The integrated receive baseband filters offer selectable bandwidth, enabling the device to receive both WCDMA and GSM-EDGE radio signals. The selectable bandwidth filter, coupled with the multiband LNA input structure, allows GSM-EDGE signals to be monitored as part of a UMTS home basestation. The transmitter uses an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise, eliminating the need for external transmit SAW filters. The fully integrated phase lock loops (PLLs) provide high performance and low power fractional-N frequency synthesis for both receive and transmit sections. Special precautions have been taken to provide the isolation demanded by frequency division duplex (FDD) systems. All VCO and loop filter components are fully integrated. The ADF4602 also contains on-chip low dropout voltage regulators (LDOs) to deliver regulated supply voltages to the functions on chip, with an input voltage of between 3.1 V and 3.6 V. The IC is controlled via a standard 3-wire serial interface with advanced internal features allowing simple software programming. Comprehensive power-down modes are included to minimize power consumption in normal use.
Rev. 0 | Page 3 of 36
ADF4602 SPECIFICATIONS
VDD = 3.1 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3.3 V and TA = 25C, 26 MHz reference input level = 0.7 V p-p. Table 1.
Parameter REFERENCE SECTION Reference Input Reference Input Frequency Reference Input Amplitude REFCLK Output (26 MHz) Output Load Capacitance Output Swing Output Slew Rate Output Duty Cycle Variation CHIPCLK Output (19.2 MHz) Output Load Capacitance Frequency Multiplication Ratio Output Swing Output Duty Cycle Variation Output Jitter Lock Time TRANSMIT SECTION I/Q Input Input Resistance Input Capacitance Differential Peak Input Voltage Input Common-Mode Voltage Baseband Filter 3 dB Bandwidth TX Gain Control Maximum Gain Gain Control Range Gain Control Resolution Gain Control Accuracy Gain Settling Time RF Specifications (High Band) Carrier Frequency Output Impedance Output Power (POUT) Output Noise Spectral Density Min Typ Max Unit Test Conditions
0.1
26 0.7 10 1.5 200 2 10
2.0 40
MHz V p-p pF V p-p V/s % pF N/A V p-p % ps rms s
Single-ended operation, dc-coupled 1
10 pF load 10 pF load Input duty cycle = 50%
48/65 1.5 2 36 50
40 48/65
10 pF load Input duty cycle = 50%
1.05
100 2 500 1.2 4.0 5 60 1/32 1.0 10 1
550 1.4
k pF mV pd V MHz dB dB dB dB dB s
Single-ended Single-ended
1 V p-p differential baseband input Average of LSB steps Any 1 dB step Any 10 dB step POUT within 0.1 dB of final value
1710 50 -8 -155 -161 -161 -163 -35 5 55 70
2170
Carrier Leakage FDD EVM FDD ACLR
MHz dBm dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc % dB dB
TM1 signal 64 DPCH 40 MHz offset 80 MHz offset 95 MHz offset 190 MHz offset POUT = -8 dBm POUT = -8 dBm 5 MHz, POUT = -8 dBm 10 MHz, POUT = -8 dBm
Rev. 0 | Page 4 of 36
ADF4602
Parameter RF Specifications (Low Band) Carrier Frequency Output Impedance Output Power (POUT) Output Noise Spectral Density Carrier Leakage FDD EVM FDD ACLR RECEIVE SECTION Baseband I/Q Output Output Common Mode Voltage Differential Output Range Output DC Offset Quadrature Gain Error Quadrature Phase Error In-Band Gain Ripple Low-Pass Filter Rejection WCDMA (Seventh Order) Min 824 50 -6 -158 -35 5 55 70 Typ Max 960 Unit MHz dBm dBc/Hz dBc % dB dB Test Conditions
TM1 signal 64 DPCH 45 MHz offset POUT = -6 dBm POUT = -6 dBm 5 MHz, POUT = -6 dBm 10 MHz, POUT = -6 dBm
1.15 1.35
1.2 1.4 4 5 100 0.3 1 0.2 30 45 84 110 14 31 55 80 12 47 90 250 200 102 90 1 1 2
1.35 1.55
0.7
V V V p-p d mV mV dB rms dB dB dB dB dB dB dB dB dB dB dB dB ns ns dB dB dB dB dB
Mode 1 Mode 2 WCDMA HPF mode GSM servo loop mode
WCDMA (Fifth Order)
GSM
@2.7 MHz @3.5 MHz @5.9 MHz @10 MHz @2.7 MHz @3.5 MHz @5.9 MHz @10 MHz @200 kHz @400 kHz @800 kHz 1.92 MHz band 100 kHz band WCDMA mode
Differential Group Delay WCDMA GSM Receiver Gain Control Maximum Voltage Gain Gain Control Range Gain Control Resolution Gain Control Step Error RF Specifications (High Band) Input Frequency Input Impedance Input Return Loss Noise Figure Maximum Input Power 3 Input IP3 Input IP2 EVM
1 dB step 10 dB step
1710 50 -20 4.0
2170
MHz dB dB dBm dBm dBm dBm dBm %
-20 -2 -7 0 53 65 8
Rev. 0 | Page 5 of 36
TX power of -8 dBm, spur-free measurement 2 Maximum LNA gain Minimum LNA gain 10 MHz and 20 MHz Offset, 59 dB gain 85 MHz and 190 MHz Offset, 59 dB gain 80 MHz offset 190 MHz offset -60 dBm input
ADF4602
Parameter RF Specifications (Low Band) Input Frequency Input Impedance Input Return Loss Noise Figure Maximum Input Power3 Input IP3 Input IP2 EVM Synthesizer Section Channel Resolution Lock Time3 DAC/GPO CONTROL DAC1 Resolution Output Range Absolute Accuracy Output LSB Step Output Capacitive Load Output Current Output Impedance DAC2 Resolution Output Range DNL INL Output Capacitive Load Output Current Output Impedance GPO1 to GPO4 Output Current Output High Voltage Output Low Voltage Switching Time LOGIC INPUTS Input High Voltage, VINH Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN LOGIC OUTPUTS (SDATA) Output High Voltage, VOH Output Low Voltage, VOL CLKOUT Rise/Fall CLKOUT Load TEMPERATURE RANGE (TA) Min 824 50 -20 4.0 -20 -2 2 5 40 7 50 200 Typ Max 960 Unit MHz dB dB dBm dBm dBm dBm dBm % kHz s Test Conditions
80 dB gain, TX power of -8 dBm Maximum LNA gain Minimum LNA gain 10 MHz and 20 MHz offset, 59 dB gain 45 MHz and 90 MHz offset, 59 dB gain 45 MHz offset -60 dBm input
5 2.3 50 25 -10 1 6 0 0.5 1.0 -5 5 2 10 2.6 0.2 1 1.2 1.2 2.1 3.3 0.6 1 10 1 +5 2.85 1 +10 3.15
bits V mV mV nF mA bits V LSB LSB nF mA mA mA V V s V V V A pF V V ns pF C
VDD > 3.15 V Any code, VDD > 3.2 V
No load No load
GPO1, GPO2, GPO3 GPO4 Maximum output current Maximum output current 5 pF load 1.8 V readback mode 4 2.8 V readback mode4
VX - 0.45 0.45 5 10 85
VX = VINT or VSUP8, IOH = 500 A IOL = 500 A
0
Rev. 0 | Page 6 of 36
ADF4602
Parameter POWER SUPPLIES Voltage Supply VDD VSUP1 VSUP2 Min Typ Max Unit Test Conditions
3.1
3.3 2.6 2.8
3.6
V V V
VSUP3 VSUP4 VSUP5
1.9 2.6 2.8
V V V
VSUP6 VSUP7 VSUP8 VINT CURRENT CONSUMPTION Transmit Current Consumption -8 dBm Output Level -28 dBm Output Level Receive Current Consumption
1 2
1.9 1.9 2.8 1.6 1.8 2.0
V V V V
Main supply input Output from internal LDO1, 10 mA rating, supply for RX VCO Output from Internal LDO2, 30 mA rating, supply for RX baseband and RX downconverter Output from internal LDO3, 10 mA rating, supply for RX LNAs Output from internal LDO4, 10 mA rating, supply for TX VCO Output from internal LDO5, 100 mA rating, supply for TX modulator, TX baseband, PA control DACs Supply input for RX synthesizer, connect to VSUP3 Supply input for TX synthesizer, connect to VSUP3 Supply input for reference section, connect to VSUP2 Supply input for serial interface control logic VDD = 3.6 V, output is matched into 50 FRF = 2170 MHz FRF = 2170 MHz
100 50 50
mA mA mA
The reference frequency should be dc coupled to the REFIN pin. It is ac-coupled internally. The noise figure measurement does not include spurious due to harmonics of the 26 MHz reference frequency. Spurs appear at integer multiples of the reference frequency (every 26 MHz), degrading the receive sensitivity by about 6 dB. 3 Guaranteed by design, not production tested. 4 Bit sif_vsup8 in Register 2 controls whether 1.8 V readback mode or 2.8 V readback mode is selected. See the Serial Port Interface (SPI) section for more details.
Rev. 0 | Page 7 of 36
ADF4602 TIMING CHARACTERISTICS
VDD = 3.1 V to 3.6 V, VGND = 0 V, TA = 25C, unless otherwise noted. Guaranteed by design but not production tested. Table 2.
Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Limit at TMIN to TMAX 62 10 10 10 31 31 10 20 20 20 Unit ns min ns min ns min ns min ns min ns min ns min ns max ns max ns max Test Conditions/Comments SEN high to write time SEN to SCLK setup time SDATA to SCLK setup time SDATA to SCLK hold time SCLK high duration SCLK low duration SEN to SCLK hold time SEN to SDATA valid delay SCLK to SDATA valid delay SEN to SDATA disabled delay
WRITE
t5
SCLK
t6
t3
SDATA W[25]
t4
W[1] W[0]
W[24]
SEN
t1
Figure 2. Serial Interface Write Diagram
READ REQUEST
READ
SCLK
t9
SDATA Q[25] Q[24] Q[1] Q[0] R[25] R[24] R[1] R[0]
07092-002
t2
t7
t10
SEN
t8
3 or more 3 OR MORE SYSCLK periods SCLK PERIODS
ADF4602 selected device DRIVES RSDATA drives SDATA
DB B releases HOST RELEASES RSDATA SDATA
Figure 3. Serial Interface Read/Write Diagram
Rev. 0 | Page 8 of 36
07092-003
ADF4602 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to GND VSUP1, VSUP2 to GND VSUP4, VSUP5, VSUP6, VSUP7, VSUP8, VSUP9 to GND VSUP3 to GND VINT to GND Analog I/O Voltage to GND Digital I/O Voltage to GND Operating Temperature Range Commercial (B Version) Storage Temperature Range Maximum Junction Temperature LFCSP JA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature Rating -0.3 V to +4 V -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V 0C to +85C -65C to +125C 150C 32C/W 240C 40 sec
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly.
ESD CAUTION
Rev. 0 | Page 9 of 36
ADF4602 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
40 39 38 37 36 35 34 33 32 31 GPO2 GPO1 VSUP6 NC REFIN REFCLK VSUP8 CHIPCLK GPO4 VDD
GPO3 1 VSUP1 2 VSUP3 3 RXLBRF 4 NC 5 RXHB2RF 6 RXHB1RF 7 RXBBI 8 RXBBIB 9 RXBBQ 10
ADF4602
TOP VIEW (Not to Scale)
30 29 28 27 26 25 24 23 22 21
DAC1 DAC2 VSUP5 TXRFGND TXHBRF TXRFGND TXLBRF TXBBQB TXBBQ VSUP4
NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR CORRECT CHIP OPERATION. IT PROVIDES BOTH A THERMAL AND ELECTRICAL CONNECTION TO THE PCB.
RXBBQB VSUP2 VINT SDATA SCLK SEN NC VSUP7 TXBBI TXBBIB
11 12 13 14 15 16 17 18 19 20
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Mnemonic GPO3 VSUP11 VSUP31 RXLBRF NC RXHB2RF RXHB1RF RXBBI RXBBIB RXBBQ RXBBQB VSUP21 VINT SDATA SCLK SEN NC VSUP71 TXBBI TXBBIB VSUP41 TXBBQ TXBBQB TXLBRF TXRFGND TXHBRF TXRFGND VSUP51 DAC2 DAC1 Function General Purpose Output 3. Digital output. This is used for external switch or PA control. Output from LDO 1. Supply for receive VCO. Nominal value of 2.6 V. 100 nF decoupling to ground is required. Output from LDO 3. Supply for receive LNA. Nominal value of 1.9 V. 100 nF decoupling to ground is required. Receive Low Band LNA Input. No Connect. Do not connect to this pin. Receive Second High Band LNA Input. Should be used for Band 2. Receive First High Band LNA Input. Should be used for Band 1. Receive Baseband I Output. Complementary Receive Baseband I Output. Receive Baseband Q Output. Complementary Receive Baseband Q Output. Output from LDO 2. Supply for receive downconverter and baseband. Nominal value of 2.8 V. 100 nF decoupling to ground is required. Serial Port Supply Input. 1.8 V should be applied to this pin. Serial Port Data Pin. This can be an input or output. Serial Clock Input. Serial Port Enable Input. No Connect. Do not connect to this pin. Transmit Synthesizer Supply Input. Connect to VSUP3 and decouple with 100 nF to ground. Transmit Baseband I Input. Complementary TX Baseband I Input. Output from LDO4. Supply for transmit VCO. Nominal value of 2.8 V. 100 nF decoupling to GND is required. Transmit Baseband Q Input. Complementary TX Baseband Q Input. Low Band Transmit RF Output. This can output in the range of 824 MHz to 960 MHz. Transmit RF Ground. Connect this pin to ground. High Band Transmit RF Output. This can output in the range of 1710 MHz to 2170 MHz. Transmit RF Ground. Connect this pin to ground. Output from LDO 5. Supply for transmit modulator, baseband, power detector, and DACs. Nominal value of 2.8 V. 100 nF decoupling to ground is required. Output from DAC2. Output from DAC1.
Rev. 0 | Page 10 of 36
07092-004
ADF4602
Pin No. 31 32 33 34 35 36 37 38 39 40 Mnemonic VDD GPO4 CHIPCLK VSUP81 REFCLK REFIN NC VSUP61 GPO1 GPO2 EPAD Function Main Supply Input. Digital Output. This is used for switch or PA control. Chip Clock Output. Reference Clock Supply Input. Connect to VSUP2, and decouple to ground with 100 nF. Reference Clock Output. Reference Clock Input. The reference is ac-coupled internally. No Connect. Do not connect to this pin. Receive Synthesizer Supply Input. Connect to VSUP3 and decouple to ground with 100 nF. Digital Output. This is used for switch or PA control. Digital Output. This is used for switch or PA control. Exposed Paddle Under Chip. This must be connected to ground for correct chip operation. It provides both a thermal and electrical connection to the PCB.
1
Y5V capacitors are not recommended for use with these pins. X7R, X5R, C0G or a similar type of capacitor should be used.
Rev. 0 | Page 11 of 36
ADF4602 TYPICAL PERFORMANCE CHARACTERISTICS
Ref Lvl 6 dBm 0 -7 dB -21 2 -28 2 -35 -42 -49 -56 -63 START: CH 0 Ref Lvl 6 dBm 64 CH/DIV CF 881.5 MHz Result Summary CPICH Slot 0 STOP: CH 511 SR 15 ksps Chan Code 0 Chan Slot 0 A LN CF 881.5 MHz Code Pwr Relative CPICH Slot 0 SR 15 ksps Chan Code 0 Chan Slot 0
-30 -35 -40 -45 +5MHz -5MHz +10MHz -10MHz
ACLR (dB)
B LN
-70
-50 -55 -60 -65
07092-005
-12
-10 -8 -6 OUTPUT POWER (dBm/3.84MHz)
-4
Figure 5. UMTS Band 5 Transmit EVM, Test Model 1, 64 DPCH, 2% EVM
Code Power Relative CF 2.1399994 GH -7 Ref 3.90 dBm Att* 0 dB -14 -21 -28 -35 -42 -49 1 VIEW A CPICH Slot 0 SR 240 ksps Chan Code 0 Chan Slot 0
Figure 8. TXHBRF Transmit ACLR vs. Output Power, Test Model 1 Signal, 10.54 dB PAR, 217 MHz
-30 -35 -40 -45 +5MHz -5MHz +10MHz -10MHz
-56 -63 Start Ch 0 Result Summary CF 2.1399994 GH CPICH Slot 0 0: -8.03 0.95 1.83 2.54 0 64 Ch/ SR 240 ksps Chan Code 5 Chan Slot 0 dBm ppm % % Carrier Freq Error Trigger to Frame IQ Imbalance Pk CDE (15 ksps) No of Active Chan RHO Timing Offset Channel Slot No Modulation Type Channel Power Abs Symbol EVM 65.98 9.642977 0.23 -50.12 44 Hz ms % dB Stop Ch 511 3DB
ACLR (dB)
-50 -55 -60 -65
07092-009
Ref 3.90 dBm Att* 0 dB
GLOBAL RESULTS FOR FRAME Total Power Chip Rate Error IQ Offset Composite EVM CPICH Slot No CHANNEL RESULTS Symbol Rate Channel Code No of Pilot Bits Channel Power Rel Symbol EVM
B
07092-006
1 CLRWR
240.00 ksps 5 0 -0.04 dB 2.43 % rms
0.99936 0 Chips 0 16QAM -19.05 dBm 7.02 % Pk
3DB
-70 -25
-20
-15 -10 -5 OUTPUT POWER (dBm/3.84MHz)
0
Figure 6. UMTS Band 1 Transmit EVM, Test Model 5, 2.5% EVM
Figure 9. TXLBRF Transmit ACLR vs. Output Power, Test Model 1 Signal, 10.54 dB PAR, 881 MHz
*RBW 30kHz *VBW 300kHz *SWT 100ms CH PWR ACP LOW ACP UP ALT1 LOW ALT1 UP
20 18 16
COMPOSITE EVM (%)
14 12
DUT DUT DUT DUT DUT
1 4 6 8 10
DUT DUT DUT DUT DUT
2 5 7 9 3
REF -12.7dBm -20 -30 -40 -50
*ATT 0dB
POS -12.698dBm
-8.08dBm -57.05dBm -57.09dBm -70.92dBm -71.41dBm
10
-60
8 6
30dB DYNAMIC RANGE <6% EVM
-70 -80
4
-90
2
-100
07092-007
-30
-25
-20 -15 -10 TXPWR_SET (dBm)
-5
0
5
-110 CENTER 2.14GHz 2.55MHz/DIV SPAN 25.5MHz
Figure 7.Transmit EVM vs. TXPWR_SET (dBm), Measured Across 10 DUTS, Four Calibration Points Applied
Figure 10. TXHBR Transmit ACLR, 2140 MHz
Rev. 0 | Page 12 of 36
07092-010
0 -35
07092-008
GLOBAL RESULTS Total PWR Chip Rate Err IQ Offset Composite EVM CPICH Slot Number CHANNEL RESULTS Symb Rate Channel Code Modulation Type Chan Pow rel. Symbol EVM
-4.57 1.04 0.79 2.04 0 15 0 QPSK 0.00 0.74
RESULT SUMMARY Carr Freq Err -92.42 Hz Trg to Frame 22.62 ae s IQ Imbalance 0.36 % Pk Code Dom Err -49.96 dB rms ( 15 ksps) Timing Offset ksps 0 Chips Chan Slot Number 0 No. of Pilot Bits 0 Chan Pow abs. dB -14.60 dBm % rms Symbol EVM 1.21 % Pk dBm ppm % % rms
-70 -14
ADF4602
MARKER 1 (T1) *RBW 30kHz -23.01dBm *VBW 300kHz 880.877403846MHz REF -10.9dBm *ATT 5dB *SWT 100ms -4.39dBm CH PWR POS -10.895dBm ACP LOW -60.63dBm -20 -58.52dBm ACP UP ALT1 LOW -72.07dBm -30 -72.13dBm ALT1 UP -40 -50 -60 -70 -80
-64 -54 0C 5MHz HIGH 25C 5MHZ HIGH 85C 5MHz HIGH 0C 5MHz LOW 25C 5MHz LOW 85C 5MHz LOW
-56
5MHz ACLR (dB)
-58
-60
-62
-90
07092-011
07092-014
07092-016
-100 -110 CENTER 881MHz 2.55MHz/DIV SPAN 25.5MHz
-66 865
870
875 880 885 FREQUENCY (MHz)
890
895
Figure 11. TXLBRF Transmit ACLR, 881 MHz
Figure 14. Transmit ACLR vs. Frequency and Temperature (Band 5), Transmit Output Power = -7 dBm
-51 -53 0C 5MHz HIGH 25C 5MHZ HIGH 85C 5MHz HIGH 0C 5MHz LOW 25C 5MHz LOW 85C 5MHz LOW
5 0 -5
MAGNITUDE (dBm)
-55
-10 -15 -20 -25 -30 -35
07092-015
5MHz ACLR (dB)
-57
-59 -61 -63
07092-012
-65 2110
2120
2130 2140 2150 FREQUENCY (MHz)
2160
2170
-40 0.1
1
10 FREQUENCY (MHz)
100
Figure 12. Transmit ACLR vs. Frequency and Temperature (Band 1), Transmit Output Power = -8 dBm
-70 0C 5MHz HIGH 25C 5MHZ HIGH 85C 5MHz HIGH 0C 5MHz LOW 25C 5MHz LOW 85C 5MHz LOW
PHASE NOISE (dBc/Hz)
Figure 15. Transmit Baseband Filter Response
-51 -53
-80 -90 -100 -110 -120 -130 -140 -150
-55
5MHz ACLR (dB)
-57
-59 -61 -63
-160 -170 1k
1940
1950 1960 1970 FREQUENCY (MHz)
1980
1990
07092-013
-65 1930
10k
100k 1M OFFSET FREQUENCY (Hz)
10M
100M
Figure 13. Transmit ACLR vs. Frequency and Temperature (Band 2), Transmit Output Power = -8 dBm
Figure 16. Transmit Synthesizer Phase Noise
Rev. 0 | Page 13 of 36
ADF4602
0.14
16 14 12 10 MIXSTEP = 10 LNASTEP = 6 GAINCAL = 8
0.12
CURRENT CONSUMPTION (A)
0.10 0.08
EVM (%)
07092-017
8 6
0.06 0.04
4
0.02
2
07092-020 07092-022 07092-021
0 -34 -32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 OUTPUT POWER (dBm/3.84MHz)
0 20
30
40 50 60 70 RECEIVE GAIN SETTING (dB)
80
90
Figure 17. Current Consumption vs. Transmit Output Power; Frequency = 2170 MHz, VDD = 3.3 V, Test Model 5 Signal, Receiver Disabled
10 0
Figure 20. Receive EVM vs. Gain; 2.84 MHz QPSK Modulated Input Signal, WCDMA Receive Baseband Filter
2.0 1.8 MIXSTEP = 6 LNASTEP = 10 GAINCAL = 8
-10
1.6
-20
MAGNITUDE (dB)
GAIN STEP (dB)
07092-018
-30 -40 -50 -60 -70 -80 -90 -100 0.01 0.1 1 FREQUENCY (MHz) 10
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 20
30
40 50 60 70 80 RECEIVE GAIN SETTING (dB)
90
100
Figure 18. Receive WCDMA Baseband Filter Response
Figure 21. Receive Gain Step Error vs. Gain Setting, 1 dB Steps, Measurement was taken by injecting known signal level and measuring the gain through the device. The gain was then stepped through all settings in 1 dB steps, and the gain step change measured in each case.
10 0 -10
25 23 20 MIXSTEP = 6 LNASTEP = 10 GAINCAL = 8
MAGNITUDE (dBm)
-30 -40 -50 -60 -70
NOISE FIGURE (dB)
07092-019
-20
18 15 13 10 8 5
-80 -90 -100 10 100 FREQUENCY (kHz) 1000
3 0 40
50
60 70 RECEIVE GAIN SETTING (dB)
80
90
Figure 19. Receive GSM Baseband Filter Response
Figure 22. Receiver Noise Figure vs. Gain. Rx Frequency = 1955 MHz
Rev. 0 | Page 14 of 36
ADF4602
20 GAIN = 80dB 18 16 NOISE FIGURE (dB) 14 12 10 8 6 4 2
07092-023
-100 25C 0C 85C GAIN = 80dB -102 -104 SENSITIVITY (dBm) -106 -108 -110 -112 -114 -116 -118
07092-046
07092-027 07092-026
TS25.104 LIMIT
0 1920
1930
1940 1950 1960 FREQUENCY (MHz)
1970
1980
-120 1918
1928
1938 1948 1958 FREQUENCY (MHz)
1968
1978
Figure 23. HB1 Receive Noise Figure vs. Frequency
Figure 26. Receive Sensitivity vs. Frequency (See the Receive Sensitivity Section for More Details)
2
16 GAIN = 80dB 14 12
NOISE FIGURE (dB)
25C 0C 85C
10MHz + 19.8MHz IP3 (dBm)
0 -2 -4 -6 -8 -10 -12 -14
25C 0C 85C
10 8 6 4 2
07092-024
-16
0 1850
1860
1870 1880 1890 FREQUENCY (MHz)
1900
1910
-18 0 10 20 30 40 50 60 70 80 RECEIVE GAIN SETTING (dB) 90 100 110
Figure 24. HB2 Receive Noise Figure vs. Frequency
Figure 27. HB1 Receive IP3, 10 MHz + 19.8 MHz vs. Gain Setting
10 GAIN = 80dB 9 8 NOISE FIGURE (dB) 7 6 5 4 3 2 1
07092-025
8
25C 0C 85C
85MHz + 190MHz IP3 (dBm)
6 4 2 0 -2 -4 -6 -8 -10 -12 -14 0 10 20 30 40 50 60 70 80 RECEIVE GAIN SETTING (dB) 90
25C 0C 85C
0 822
827
832 837 842 FREQUENCY (MHz)
847
100
110
Figure 25. LB Receive Noise Figure vs. Frequency
Figure 28. HB1 Receive IP3, 85 MHz + 190 MHz vs. Gain Setting
Rev. 0 | Page 15 of 36
ADF4602
110 105 100 95 25C 0C 85C 16 14 12 10 8 6 4 2 0 -2 -4 -6 -8 -10 0 10 20 30 40 50 60 70 80 RECEIVE GAIN SETTING (dB) 90 100 110 0 10 20 30 40 50 60 70 80 RECEIVE GAIN SETTING (dB) 90 100 110
07092-031 07092-033 07092-032 07092-028
190MHz IP2 (dBm)
90 85 80 75 70 65 60 55 50
10MHz + 19.8MHz IP3 (dBm)
25C 0C 85C
-12
Figure 29. HB1 Receive IP2, 190 MHz vs. Gain Setting
8 6 4 25C 0C 85C
Figure 32. LB Receive IP3, 10 MHz + 19.8 MHz vs. Gain Setting
16 14 12 25C 0C 85C
2 0 -2 -4 -6 -8 -10 -12
07092-029
45MHz + 22.5MHz IP3 (dBm)
80MHz + 40MHz IP3 (dBm)
10 8 6 4 2 0 -2 -4 -6 -8 -10 0 10 20 30 40 50 60 70 80 RECEIVE GAIN SETTING (dB) 90 100 110
-14 0 10 20 30 40 50 60 70 80 RECEIVE GAIN SETTING (dB) 90 100 110
Figure 30. HB2 Receive IP3, 80 MHz + 40 MHz vs. Gain Setting
100 25C 0C 85C
Figure 33. LB Receive IP3, 45 MHz + 22.5 MHz vs. Gain Setting
100 90 25C 0C 85C
90
80
80MHz IP2 (dBm)
45MHz IP2 (dBm)
07092-030
80
70
70
60
60
50 50 40
40 0 10 20 30 40 50 60 70 80 RECEIVE GAIN SETTING (dB) 90 100 110
30 0 10 20 30 40 50 60 70 80 RECEIVE GAIN SETTING (dB) 90 100 110
Figure 31. HB2 Receive IP2, 80 MHz vs. Gain Setting
Figure 34. LB Receive IP2, 45 MHz vs. Gain Setting
Rev. 0 | Page 16 of 36
ADF4602 THEORY OF OPERATION
TRANSMITTER DESCRIPTION
TESTI, SWAP_I
TXBBI TXBBIB LPF INTEGRATED BALUN
LB ONLY DIVIDER /2 DIVIDER AND QUAD GEN /2 -90 DEGREES TXBs
PA TX OUTPUT
TXBBQ TXBBQB LPF
TESTQ, SWAP_Q
GAIN CONTROL
07092-034
TXPWR_SET[11:0]
Figure 35. Transmitter Block Diagram
The ADF4602 contains a highly innovative low noise variable gain direct conversion transmitter architecture, that removes the need for external transmit SAW filters. The direct conversion architecture significantly reduces the risk of transmit harmonics across all bands due to the simplified nature of the frequency plan. See Figure 35 for a block diagram.
VOLTS I OR Q
I/Q Baseband
The baseband interface for the I and Q channels is a differential, dc-coupled input, supporting a wide range of input commonmode voltages (VCM). The allowable input common-mode range is 1.05 V to 1.4 V. The maximum signal swing allowed is 550 mV peak differential. This corresponds to a 1.1 V peak-to-peak differential on either the I or Q channel. Figure 36 shows a graphical definition of peak differential voltage and VCM. The baseband input signals pass through a second order Butterworth filter prior to the quadrature modulator. The cutoff frequency is 4 MHz. This gives some rejection of the DAC images. The filter also helps to suppress any spurious signals that might be coupled to the baseband terminals on the PCB. For ease of PCB routing between the ADF4602 and the transmit DAC, the I and Q differential inputs can be internally swapped. For user test purposes, the I and Q inputs can also be internally shorted together and a dc offset applied. This produces a large carrier at the RF output, which is useful for signal path integrity testing.
IB OR QB PEAK V DIF
07092-035
VCM TIME
Figure 36. Transmit Baseband Input Signals
Rev. 0 | Page 17 of 36
ADF4602
I/Q Modulator
The I/Q modulator converts the transmit baseband input signals to RF. Calibration techniques are used to maintain accurate IQ balance and phase across frequency and environmental conditions, thus ensuring that 3GPP carrier leakage and EVM and ACLR requirements are met with good margin under all conditions. The on-chip calibrations are carried out during the transmit PLL lock time specified and are self-contained, requiring no additional input from the user. The modulator has an 80 dB gain control range, programmable in 1/32 of a decibel step. The 12-bit word txpwr_set[11:0] in Register 28 controls the transmit output power. The setting is referenced to a full-scale (500 mV peak differential) sine wave signal applied to the transmit baseband inputs. To calculate the output power when a WCDMA modulated signal with a certain peak-to-average ratio is applied, Equation 1 should be used. Output Power (dBm/3.84 MHz) = txpwr(dBm) - PAR(dB) (1) where txpwr(dBm) is the txpwr_set[11:0] value converted to dBm, and PAR is the peak-to-average ratio of the WCDMA signal. For example, if an output power of -8 dBm is required for a WCDMA signal with a peak-to-average ratio of 10 dB txpwr(dBm) = -8 dBm + 10 dB = +2 dBm The current consumption of the modulator scales with output power. When the TX power is backed off from maximum, the transceiver benefits from lower power dissipation. user because most power amplifiers (PAs) are singled-ended. This situation would normally require additional external matching components or a differential to single-ended SAW filter structure. With the ADF4602, the SAW filter is not necessary, and the required low loss balun is fully integrated, converting the differential internal signals to a single-ended 50 output, thus allowing easy interfacing to the PA. The high band output is available at the TXHBRF pin, and the low band output is available at the TXLBRF pin. These are directly connected to a 50 load, if necessary, and do not require ac-coupling.
DACS
The ADF4602 integrates two DACs that are designed to interface to an external PA to control reference or bias nodes within the PA. If this function is not required, the DACs are used for any general purpose or powered down if not required. DAC1 is a 5-bit voltage output DAC. The output range is from 2.3 V to 3.15 V (for VDD > 3.15 V). The DAC1 output stage is supplied directly from VDD, with the capability to supply 10 mA of current to within 50 mV of VDD. For high accuracy, the DAC reference is supplied from LDO5, which is internally trimmed to 25 mV accuracy. The DAC1 output is set by the PADAC1[4:0] word. DAC2 is a 6-bit voltage output DAC with a range from 0 V to 2.8 V. LDO5 supplies both the reference voltage and full-scale output voltage for DAC2. The output voltage is set by the padac2_ow[5:0] word. The dacgpo_owen bit must also be set high if control of DAC2 is required. Both DACS are powered down by writing the code, 0x0, to the respective control register.
VCO Output
The TX VCO output is fed to a tuned buffer stage and then to the quadrature generation circuitry. The tuned buffer ensures that minimum current and LO related noise is generated in the VCO transport. This action is transparent to the user. The quadrature generator creates the highly accurate phased signals required to drive the modulator and also acts as a divide-by-2. In low band, an additional divide-by-2 is used in the VCO transport path, which is bypassed in high band. This is done to minimize the VCO tuning range required to cover all the bands. The phase accuracy of the signals is important in ensuring good modulation quality and accurate output power. An on-chip calibration ensures that the phased signals are exactly 90 out of phase. This calibration runs each time the frequency is changed or if the txpwr_set[11:0] word is written to. If the temperature of the device changes, this calibration should be updated. To run the calibration, the user should simply write to the txpwr_set[11:0] word for each five degree change in temperature, or update the value regularly (every few seconds) between WCDMA frames or timeslots. This ensures that good EVM and accurate output power are maintained as the temperature of the device changes.
GENERAL PURPOSE OUTPUTS
Four general-purpose outputs (GPOs) are provided on the ADF4602. These are used to control PA bias modes or, more commonly, the GPOs are used to control external RF front-end switches in the transmit/receive path. The GPOs are simple 3 V digital output drivers. GPO1 to GPO3 are capable of supplying a maximum current of 2 mA, whereas GPO4 can supply up to 10 mA. For operation of the GPOs, Bit dacgpo_owen must be set to 1. The GPOs are then controlled via the gpo_ow[3:0] word.
RECEIVER DESCRIPTION
The ADF4602 contains a fully integrated direct conversion receiver designed for multiband WCDMA femtocell applications. High performance, low power consumption, and minimal external components are the key features of the design. Figure 37 shows a block diagram of the receiver, which consists of three LNA blocks for multiband operation, high linearity I/Q mixers, advanced baseband channel filtering, and a DC offset compensation circuit.
TX Output Baluns
The baseband input, modulator, and all associated circuitry are fully differential to maintain high signal integrity and noise immunity. However, a differential output is not optimal for the
Rev. 0 | Page 18 of 36
ADF4602
LNA 0dB TO 18dB 3 x 6dB STEPS RxEN[1:0] MIXER TRANSCONDUCTANCE 18dB TO 30dB (WCDMA) 27dB TO 39dB (CDMA) 2 x 6dB STEPS ACTIVE FILTER CHANGES 0dB TO 18dB 0dB TO 18dB 3 x 6dB STEPS 3 x 6dB STEPS VGA -6dB TO +18dB 24 x 1dB STEPS
RXBBI RXHB2RF BPF HIGH BAND LNA 2 RXHB1RF BPF HIGH BAND LNA 1 RXLBRF BPF LOW BAND LNA LPF LPF LPF VCMSEL GAIN CONTROL RXBW_TOGGLE
07092-036
LPF DAC /2 OR /4 DAC
LPF
LPF ADC PROGRAMMABLE OFFSET CONTROL ADC
RXBBIB
RXBBQ RXBBQB
RxGAIN[6:0]
Figure 37. Receiver Block Diagram
LNAs
The ADF4602 contains three tunable RF front ends suitable for all major 3GPP frequency bands. Two are suitable for high band operation in the region 1700 MHz to 2170 MHz. One is suitable for operation from 824 MHz to 960 MHz. Thus, the three integrated LNAs offer the designer the opportunity to create multiband and regional specific variants with no additional components. LNA power control and internal band switching is fully controlled by the serial interface. The ADF4602 LNAs are designed for 50 single-ended inputs, thus further simplifying the front-end design and providing easy matching with minimal components. Typically, a twocomponent match is required: a series and shunt inductor. Within the LNA, the signal is converted to a differential path for signal processing in subsequent blocks within the receive signal chain. Interstage RF filtering is fully integrated, ensuring that external out-of-band blockers are suitably attenuated prior to the mixer stages. The LNA characteristic is designed to provide additional filtering at the transmitter frequency offset. The LNAs are enabled by programming bits rxbs[1:0] in Register 1. LNA input HB1 should be used for UMTS Band 1 operation, and HB2 should be used for UMTS Band 2 operation.
Quadrature drive is provided to the mixers from the receiver synthesizer section by the VCO transport system, which includes a programmable divider, so that the same VCO is used for both high and low bands. Excellent 90 quadrature phase and amplitude match are achieved by careful design and layout of the mixers and VCO transport circuits.
Baseband Section
The ADF4602 baseband section is a distributed gain and filter function designed to provide a maximum of 54 dB gain with 60 dB gain control range. Through careful design, pass band ripple, group delay, signal loss, and power consumption are kept to a minimum. Filter calibration is performed during the manufacturing process, resulting in a high degree of accuracy and ease of use. Three baseband filters are available on the ADF4602, as shown in Table 5. Bits rxbw_toggle[2:0] are used to select the mode of operation. The seventh order WCDMA filter with 1.92 MHz cutoff ensures that good attenuation of the adjacent channel should be used to meet blocking/adjacent channel selection specifications in femtocell applications. The GSM filter has a 100 kHz cut-off and is intended for use as a monitoring receiver in a home base station. The fifth order WCDMA filter provides less attenuation of the adjacent channel, so it should not be used in femtocell applications. The I and Q channels can be internally swapped, thus allowing optimum PCB routing between radio and analog baseband. This is achieved using the swapi and swapq bits. Table 5. Receive Baseband Filter Modes
Mode Seventh Order WCDMA Fifth Order WCDMA GSM Filter Cutoff Frequency (fC) 1.92 MHz 1.92 MHz 100 kHz
Mixers
High linearity quadrature mixer circuits are used to convert the RF signal to baseband in-phase and quadrature components. Although not shown in Figure 37, two mixer sections exist: one optimized for the high band LNA outputs and one optimized for the low band. The high band and low band mixer outputs are combined and then driven directly into the first stage of the baseband low-pass filter, which also acts to reduce the level of the largest blocking signals, prior to baseband amplification.
Rev. 0 | Page 19 of 36
ADF4602
The receive baseband outputs have a programmable common mode voltage of 1.2 V or 1.4 V, selectable via the vcmsel bit in Register 15.
BLOCK GAIN (dB)
120 110 100 90 80 70 60 50 40 30 20 10 0 -10 0 10 20 30 40 50 60 70 80 90 REQUESTED Rx GAIN (dB) 100 110 120 RF GAIN BASEBAND GAIN CHIP GAIN
07092-037 07092-038
MIXSTEP = 10 LNASTEP = 6 GAINCAL = 8
Gain Control
Gain control is distributed throughout the receive signal chain as shown in Figure 39. The RF front end contains 30 dB of control range: 18 dB in the LNA and 12 dB in the mixer transconductance stage. The two baseband active filter stages each provide 18 dB of gain control range in 6 dB steps. Filter characteristics (ripple and group delay) are best conserved if the active filter stages have equal gain. This results in a total of 36 dB gain control in 4x 12 dB steps for the filter stage. The variable gain amplifier (VGA) implements 24 dB of gain controllable in 1 dB steps. The base gain of the mixer is 18 dB, and the base gain of the VGA is -6 dB. This gives a total of 102 dB gain with 90 dB of gain control range. The base gain of the mixer stage is 18 dB in WCDMA mode and 27 dB in GSM mode.
Figure 38. Gain Distribution Between RF and Baseband Blocks for Default Setting
50 45 40 35
BLOCK GAIN (dB)
MIXSTEP = 10 LNASTEP = 6 GAINCAL = 8
LNA GAIN MIXER GAIN FILTER GAIN VGA GAIN
Table 6. Receive Gain Control in WCDMA mode
Stage LNA Mixer Filter VGA Gain Control 0 dB to +18 dB +18 dB to +30 dB (WCDMA) +27 dB to +39 dB (GSM) 0 dB to +36 dB -6 dB to +18 dB Control Steps 3 x 6 dB steps 2 x 6 dB steps 3 x 12 dB steps 24 x 1 dB steps
30 25 20 15 10 5 0 -5 -10 0 10 20 30 40 50 60 70 80 90 REQUESTED Rx GAIN (dB) 100 110 120
To simplify programming and to ensure optimum receiver performance and dynamic range, the user simply programs the total desired receive gain in dB via the rx_gain[6:0] bits in Register 11. The ADF4602 then decodes the gain setting and automatically distributes the gain between the various blocks. To allow some flexibility, predefined user inputs control the gain threshold points at which the LNA and mixer gain steps occur. Bit settings mixstep[3:0] and lnastep[3:0] control the mixer and LNA gain threshold steps, respectively. An Excel spreadsheet detailing the receive gain decode system is available from Analog Devices, Inc., on request. Figure 38 shows an example gain distribution profile.
Figure 39. More Detailed Gain Distribution Profile
In addition, a gain calibration setting in Register 15 (gaincal[4:0]) is used to account for losses in the RF front end. The total gain in the ADF4602 is given by ReceiveGain = rxgain[6:0] - gaincal[4:0] + X (2) where X = 8 in WCDMA filter mode, and X = 17 in GSM filter mode. Rxgain[6:0] is the receive gain programmed in Register 11. Gaincal[4:0] is the gain calibration setting in Register 15, and is calculated using the following formula: gaincal[4:0] = 8 - front_end_losses (3) where front_end_losses is the loss in the receive path due to duplexers/switches. This is useful for referencing the programmed gain to the antenna and accounting for any losses in the path. For example, if the total receive front-end loss is 2 dB, the user should program gaincal[4:0] to 6 dB. If the user then requestes 80 dB of gain by programming rxgain[6:0] to 80 dB, the ADF4602 uses Equation 4 to give ReceiveGain = 80 - 6 + 8 = 82 dB 82 dB is the receive gain used internally by the ADF4602. (4)
Rev. 0 | Page 20 of 36
ADF4602
DC Offset Compensation
Due to the very high proportion of the total system gain assigned to the analog baseband function, compensating for dc offsets is an inherent part of any direct conversion solution. DC offsets are characterized as falling into two categories: static or slow varying and time varying The ADF4602 architecture has been designed to reduce the amount of time varying dc offsets. The device also includes a dc offset control system. The control system consists of ADCs at the baseband output to digitize dc offsets: a digital signal processing block where the characteristics of the loop are programmed for customization of the loops transfer function, and trim DACs that are used to introduce the error term back into the signal path. The offset control transfer function can either be programmed to act as a servo loop that is automatically triggered by a gain change or as a high-pass filter (HPF) with an automatic fast settling mode that is also triggered by a gain change. Parameters of the servo loop, high-pass filter, and fast settling mode are set by the initial ADF4602 programming. In operation, the dc offset control system is fully automatic and does not require any external programming. Recommended default programming conditions for the dc offset compensation loop are shown in the Register Description section.
SERIAL INTERFACE 1.8V LDO 1 LDO 2 LDO 3 LDO 4 LDO 5 RX BASEBAND AND RX VCO MIXERS RX LNAs TX VCO TX MOD TX BB PWR DET DACs RX PLL TX PLL REF PATH REF OP (SER INT READ) 2.8V
VINT
VBAT
VSUP1 C1
VSUP2 C2
VSUP3
VSUP4 C4
VSUP5 C5
VSUP6
VSUP7
VSUP8
DIGITAL 1.8V SUPPLY
1.9V C3 C6 C7
ANALOG BB OR VSUP2
07092-039
Figure 40. Power Management Block
VINT supplies the serial interface enabling register data preservation with minimum current consumption during power-down. This should be supplied with 1.8 V externally. The five LDOs are individually powered up/down via bits ldoen[4:0] in Register 1. Table 7 summarizes the supply strategy. Note that the reference path (VSUP8) supply is supplied from an external source or the internal VSUP2. The external supply option may be convenient so that the entire reference path can be shut down by collapsing a single supply. VSUP8 can also be programmed to supply the voltage used for serial interface readback. See the Serial Port Interface (SPI) section for more information. Table 7. Power Management Strategy
Pin VINT VDD VSUP1 VSUP2 VSUP3 VSUP4 VSUP5 Connection External External Internal LDO1 Internal LDO2 Internal LDO3 Internal LDO4 Internal LDO5 Usage Serial interface control logic Main device supply, DAC1 Receive VCO Receive baseband and down-converter Receive LNAs Transmit VCO Transmit baseband, modulator, DAC2, and GPOs Receive synthesizer Transmit synthesizer Reference path, reference buffer outputs; Optional: serial interface readback Volts 1.8 V 3.3 V 2.6 V 2.8 V 1.9 V 2.6 V 2.8 V
POWER MANAGEMENT
The ADF4602 contains integrated power management requiring two external power supplies: 3.3 V VDD and 1.8 V VINT. Figure 40 shows a block diagram. VDD supplies the five integrated low drop-out regulators (LDOs), VSUP1 to VSUP5, that are used to supply the vast majority of the internal circuitry. VSUP6, VSUP7, and VSUP8 supply the receive PLL, transmit PLL, and reference block, respectively. These nodes require external connections to ensure good supply isolation and ensure a minimum level of interference between the PLL/reference blocks and the rest of the transceiver. VSUP6 and VSUP7 should be connected to VSUP3, whereas VSUP8 should be connected to VSUP2. Each node, VSUP1 to VSUP8, should be externally decoupled to ground with a 0.1 F capacitor. Y5V capacitors are not recommended for use here. X7R, X5R, C0G, or a similar type of capacitor should be used.
VSUP6 VSUP7 VSUP8
Connect to VSUP3 Connect to VSUP3 VSUP2 or external
1.9 V 1.9 V 2.8 V
Rev. 0 | Page 21 of 36
ADF4602
FREQUENCY SYNTHESIS
The ADF4602 contains two fully integrated programmable frequency synthesizers for generation of transmit and receive local oscillator (LO) signals. The design uses a fractional-N architecture for low noise and fast lock-time. The fractional-N functionality is implemented with a third order - modulator. Figure 41 shows a block diagram of the synthesizer architecture.
LOOP FILTER FREF PFD C P VCO FVCO : 3.4GHz TO 4.4GHz RANGE /2 LPF
When the high band is enabled, the programmed frequency is equal to the LO frequency. For low band operation, the programmed frequency should be set to 2x the desired LO frequency. The transmit and receive synthesizers are enabled by setting Bit txsynthen and Bit rxsynthen in Register 1, respectively.
Reference Path
The ADF4602 requires a 26 MHz reference frequency input. A VCTCXO is used to provide this. The reference input is accoupled internally, so external ac coupling is not necessary. The 26 MHz reference is internally buffered and distributed to the respective blocks, such as the synthesizer PFD inputs. Figure 42 shows a block diagram.
PHASE FREQUENCY DETECTOR AND CHARGE PUMP 50kHz STEP DIVIDERS - VCO FREQ CAL AND AMPLITUDE CONTROL
DIGITAL DECODE
07092-040
RxFREQ[15:0]
Figure 41. Frequency Synthesizer Block Diagram
The ADF4602 provides two buffered outputs: a buffered version of the 26 MHz reference on Pin REFCLK and a 19.2 MHz WCDMA chip clock on Pin CHIPCLK. The 19.2 MHz chip clock is a multiple of the 3.84 MHz chip rate used in WCDMA. Thus, it can be used to clock ADCs/DACs elsewhere in the system. The chip clock is generated by an integrated PLL and contains no user settings. Both outputs are slew rate limited and produce low swing digital outputs. The buffers contain their own 1.5 V regulator circuits to improve isolation and minimize unwanted supply noise. The 26 MHz and 19.2 MHz buffer outputs are enabled or disabled by programming Bit refclken and Bit chipclken (Register 1).
26MHz CLOCK DISTRIBUTION VSUP8 REFIN (26MHz)
All necessary components are fully integrated for both transmit and receive synthesizers, including loop filters, VCOs, and tank components. The VCOs run at 2x the high band frequency and 4x the low band frequency. The dividers are external to the synthesizer loop. This minimizes VCO leakage power at the desired frequency and tuning range requirements of the VCO. The VCOs use a multiband structure to cover the wide frequency range required. The design incorporates both frequency and amplitude calibration to ensure that the oscillator is always operating with its optimum performance. The calibrations occur during the 200 s PLL lock time and are fully self contained, requiring no user inputs. The charge pump and loop filter are internally trimmed to remove variations associated with manufacture and frequency. This process is fully automated. To aid simplified programming, the ADF4602 contains a frequency decode table for the synthesizers, meaning the programmer is not concerned with the internal operation of the counters and fractional-N system. Frequency step sizes of 50 kHz are possible with both transmit and receive synthesizers. The programming words rxfreq[15:0] and txfreq[15:0] set the frequency in 50 kHz steps from 0 MHz to 3276.75 MHz. Note that the synthesizers do not cover this full range. The frequency range for each synthesizer in high and low bands is given in the Specifications section.
REFCLK 1.5V REFCLKEN PLL 1.5V REG VSUP8 CHIPCLKEN VSUP8 VSUP8
07092-041
REG
CHIPCLK
Figure 42. Reference Path Block Diagram
All reference sections are powered from VSUP8, which can safely be removed from the chip in isolation, to enter a low current power-down mode. Calibration data is not lost, but the reference frequency ceases to exist. As soon as VSUP8 is reapplied, oscillation begins. This is visible at the buffer outputs, as long as they were previously enabled.
Rev. 0 | Page 22 of 36
ADF4602 SERIAL PORT INTERFACE (SPI)
The ADF4602 contains internal registers that are used to configure the device. The three-wire serial port interface provides read and write access to the internal registers. For write, read requests, and read operations, 26-bit transfers are used. The MSB of all words are transferred first. The read request format has the same address structure as the write format but does not contain a data field. Padding is used to maintain the 26-bit word length. The readback format is the same as the word format during a write. Again, padding is used to maintain the 26-bit word length. Table 9. SPI Chip Select Code
CS[2] CS[1] 0 0 All other permutations CS[0] 1 Device ADF4602 Reserved
Format
Figure 43 shows the format of the register write. This consists of a 5-bit address and 16-bit data words. The exception is register A1 = 00000, where the lower data byte is used as an 8-bit subaddress. In total, this creates 31 16-bit registers and 256 8-bit registers. The 31 16 bit registers are referred to in the text as "Register 31" for example, while the 256 8-bit sub registers are referred to as "Register 0.144". OP is a 2-bit code specifying the type of operation being performed (see Table 8 for more information). The chip select code, CS, is a 3-bit field indicating which device on the bus is being programmed. For the ADF4602, CS should be set to 001 (D2, D1, D0). Table 8. SPI Operation Code
OP[1] 0 0 OP[0] 0 1 Operation Write Set Description Normal register write. Register bits corresponding to 1s in the data word are set. Other bits are not modified. Register bits corresponding to 1s in the data word are cleared. Other bits are not modified. Register read request.
OPERATION AND TIMING
SCLK, SDATA, and SEN are used to transfer data into the ADF4602 registers. Data is clocked into the register, MSB, first on the rising edge of each SCLK. The data is transferred to the selected register address on the rising edge of SEN. See Figure 2 and Figure 3 for timing information.
Read
Figure 3 shows a read operation. First, a read request is written by the host to the ADF4602. SEN must remain high for at least three SCLK periods between the read request operation and the following read operation. The host must release the SDATA line during this period. The ADF4602 takes control of SDATA, and the read operation commences when the host device drives SEN low. The SDATA output voltage during readback is set to 1.8 V or 2.8 V. Bit sif_vsup8 (Register 2) controls this. A 0 in this bit configures the device to use the 1.8 V VINT supply, whereas a 1 configures the 2.8 V VSUP8 supply. After power-up or after a soft reset, the ADF4602 defaults to 2.8 V readback mode.
1
0
Clear
1
1
Read
OPERATION WRITE REGISTER 1 TO 31 W[25:0] WRITE REGISTER 0 W[25:0] READ REQUEST REGISTER 1 TO 31 Q[25:0] READ REQUEST REGISTER 0 Q[25:0] READ REGISTER 1 TO 31 Q[25:0] READ REGISTER 0 Q[25:0]
BIT POSITION 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA D[15:0] DATA D[7:0] SUBADDRESS A2[7:0] RANDOM PADDING P[15:0] RANDOM PADDING P[7:0] DATA D[15:0] DATA D[7:0] SUBADDRESS A2[7:0] SUBADDRESS A2[7:0] 9 8 7 6 5 4 3 2 1 CS [2:0] CS [2:0] CS [2:0] CS [2:0] CS [2:0] CS [2:0]
07092-042
0
ADDRESS A1[4:0] ADDRESS A1 = 00000 ADDRESS A1[4:0] ADDRESS A1[4:0] ADDRESS A1[4:0] ADDRESS A1 = 00000
OP [1:0] OP [1:0] OP [1:0] OP [1:0]
OP = 11
OP = 11
Figure 43. SPI Register Write Format
Rev. 0 | Page 23 of 36
ADF4602 REGISTERS
REGISTER MAP
GENERAL USER REGISTERS A1 1 2 D15 D14 D13 rxen D12 refclk en D11 chipclk en D10 D9 D8 ldoen[4:0] D7 D6 D5 txen D4 txbs D3 txsynth en D2 D1 D0 rxsynth en reset_ soft DEFAULT1 R/W 0x2FFD 0x0002 W W
rxbs[1:0] sif_ vsup8
RECEIVER USER REGISTERS A1 10 11 12 13 14 15 rfskip[3:0] osadc2x[3:0] nint3[3:0] vcmsel sdmen[3:0] nper2[3:0] nint2[3:0] swapq swapi rxbw[2:0] mixstep[3:0] nper1[3:0] nint1[3:0] gaincal[4:0] D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT1 R/W 0x9858 rxgain[6:0] lnastep[3:0] nper0[3:0] nint0[3:0] sdmosr 0x0000 0x0FA6 0x103E 0xEE53 0x0890 W W W W W W
rxfreq[15:0]
TRANSMITTER USER REGISTERS A1 21 22 26 28 31 dacgpo _owen D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 cmmod D5 D4 D3 D2 D1 D0 DEFAULT1 R/W 0x001F 0x8000 0x0000 cntrl_ mode nvmld 0x0001 0x0000 W W W W W
test_I/swap_I gpo_ow[3:0]
test_Q/swap_Q
gain_blanksel [1:0] padac2_ow[5:0]
vcm_sat_thres[5:0] padac1[4:0]
txfreq[15:0] txpwr_set[11:0]
SUB-ADDRESS REGISTERS A1 0 0 0 0 0 0 0 0 0 A2 144 151 153 155 165 170 171 174 175 buff_value[7:0] reserved[7:0] en_mix[3:0] buffstate vsup2[7:0] reserved[7:0] reserved[7:0] reserved[7:0] D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT1 R/W 0x06 0x6F 0x85 0x78 0x20 0xF0 0x04 2 0x5F 3 0x14 W W W W W W W W W
reserved[1:0]
NOTES 1THESE ARE RECOMMENDED DEFAULT SETTINGS THAT SHOULD BE PROGRAMMED INTO THE REGISTERS. 2DEFAULT SHOWN IS FOR BAND 1 OPERATION. SET TO 0x00 IF TRANSMIT FREQUENCY < 21100MHz. 3DEFAULT SHOWN IS FOR BAND 1 OPERATION. SET TO 0x50 IF TRANSMIT FREQUENCY < 21100MHz.
Figure 44. Register Map
Rev. 0 | Page 24 of 36
07092-043
ADF4602
REGISTER DESCRIPTION
Table 10. General User Registers
Register 1, A1 Bit 13 12 11 [10:6] Bit Name rxen refclken chipclken ldoen Description Set this bit high to enable the receiver. A low here disables the receiver. Setting this bit high enables the 26 MHz reference output buffer. Setting this bit high enables the19.2 MHz chip clock output buffer. The on-chip LDOs are powered down individually. For normal operation all LDOs should be enabled (Bits[10 : 6] = [11111]) Mode ldoen[10:6] 1 XXXX1 VSUP1 2.6 V enable XXX1X VSUP2 2.8 V enable XX1XX VSUP3 1.8 V enable X1XXX VSUP4 2.6 V enable 1XXXX VSUP5 2.8 V enable Setting this bit high enables the transmitter. This bit controls which of the transmit outputs is in use. 0 = low band (TXLBRF), 1 = high band (TXHBRF). Setting this bit high enables the transmit synthesizer. These bits control the receiver band select. rxbs[2:1] Operation 00 Reserved 01 Low band enable (RXLB) 10 High Band 1 enable (RXHB1) (default) 11 High Band 2 enable (RXHB2) Setting this bit high enables the receive synthesizer The serial port readback (SDATA) output voltage is changed from 1.8 V to 2.8 V with this bit. 0 = use 1.8 V VINT supply, 1 = use 2.8 V VSUP8 supply. After power-up or after a soft reset, the ADF4602 defaults to 2.8 V readback mode. A rising edge on this bit starts a 50 s reset pulse for the full chip. This bit is self clearing. It is recommended that a soft reset be performed after power-up.
5 4 3 [2:1]
txen txbs txsynthen rxbs
2, A1
0 1
rxsynthen sif_vsup8
0
1
reset_soft
X = don't care.
Rev. 0 | Page 25 of 36
ADF4602
Table 11. Receiver User Registers
Register 10, A1 Bit [15:0] Bit Name rxfreq Description These bits set the receive synthesizer frequency in 50 kHz steps from 0 MHz to 3276.75 MHz. For the high bands this is equal to the channel frequency, and for the low bands it is 2x the channel frequency. For example: Bit 15 to Bit 0 (Hex) HB1, HB2 Synthesizer Frequency LB Synthesizer Frequency 0x9470 1900 MHz 950 MHz 0x9858 1950 MHz 975 MHz These bits set the receiver gain in conjunction with the gaincal[4:0] setting in register 15. LSB = 1 dB. 0x00 = 0dB, 0x7F = 127 dB. Gain = rxgain - gaincal + X where X is 8 in WCDMA mode and 17 in GSM mode. The mode is selected by the rxbw bits in Register 15. With mixstep = 6 and lnastep = 10, the valid range for rxgain is from 12 dB to 102 dB. Settings outside of these are clipped at 12 dB and 102 dB. See Figure 38 for an example. Skip offset control state when no RF gain step occurred for State 3 to State 0. Default = 0x0 = 0. - modulator enable for State 3 to State 0. Default = 0xF = 15. Gain decode threshold for mixer gain reduction step. LSB = 4 dB steps. Default = 0xA = 10. Gain decode threshold for LNA gain reduction step. LSB = 4 dB steps. Default = 0x6 = 6. Offset measurement ADC range for State 3 to State 0. Default = 0x1 = 1. State duration for State 2. Default = 0x0 = 0. State duration for State 1. Default = 0x3 = 3. State duration for State 0. Default = 0xE = 14. Integrator time constant for State 3. Default = 0xE = 14. Integrator time constant for State 2. Default =0xE = 14. Integrator time constant for State 1. Default = 0x5 = 5. Integrator time constant for State 0. Default = 0x3 =3. This sets the receive baseband output common-mode voltage. 0 = 1.2 V, 1 = 1.4 V. Setting this bit high swaps the differential Q outputs, RXBBQ and RXBBQB. Setting this bit high swaps the differential I outputs, RXBBI and RXBBIB. This bit controls the receive baseband filter bandwidth. rxbw [8:6] Filter Mode 000 Fifth order WCDMA filter (not recommended for femtocells) 010 Seventh order WCDMA filter (recommended WCDMA filter for femtocells) 111 GSM filter Else Reserved These bits are used for calibration of front-end loss. LSB = 1 dB, 0x00 = 0 dB, 0x1F = 31 dB. It is used in the calculation of the receive gain. See rxgain in Register 11. If not used for calibration, this should be set to 8 in WCDMA mode and 17 in GSM mode. Offset loop - modulator over sampling ratio. 1 = 4x, 0 = 2x (default)
11, A1
[6:0]
rxgain
12, A1
13, A1
14, A1
15, A1
[15:12] [11:8] [7:4] [3:0] [15:12] [11:8] [7:4] [3:0] [15:12] [11:8] [7:4] [3:0] 11 10 9 [8:6]
rfskip sdmen mixstep lnastep osadc2x nper2 nper1 nper0 nint3 nint2 nint1 nint0 vcmsel swapq swapi rxbw
[5:1]
gaincal
0
sdmosr
Rev. 0 | Page 26 of 36
ADF4602
Table 12. Transmitter User Registers
Register 21, A1 Bit [12:11] Bit Name test_I/swap_I Description These bits allow various options on the I inputs as detailed in the following table: Bits Function 00 Normal operation 01 Swap I differential inputs for ease of PCB routing to DAC 10 Zero input on I inputs 11 DC offset applied to I inputs; creates large carrier at RF These bits allow various options on the Q inputs as detailed in the table below: Bits Function 00 Normal operation 01 Swap Q differential inputs for ease of PCB routing to DAC 10 Zero input on Q inputs 11 DC offset applied to Q inputs: creates large carrier at RF During a transmit gain change, some spectral splatter may occur at the output of the transmitter. These bits allow the input baseband signal at the input to the low-pass filter to be blanked for a short period, to reduce the spectral splatter observed during the gain change. gain_blanksel[8:7] Operation 00 Default setting; no blanking 01 230 ns blanking 10 540 ns blanking 11 850 ns blanking This bit adjusts the internal modulator common-mode setting. It should be set to 0. Setting this bit to 1 results in reduced power consumption but degrades transmit linearity. This bit should be set to 0x1F for normal operation. Setting this bit high allows the user to have manual control over DAC2 and GPO1 to GPO4. These bits allow manual control of GPO 1 to GPO 4. Bit dacgpo_owen must be set to 1 to allow this mode of operation. Each bit controls one of the GPOs as per the following table. This allows all possible permutations of GPO output combinations. gpo_ow[14 :11] 1 Mode XXX1 GPO1 high XX1X GPO2 high X1XX GPO3 high 1XXX GPO4 high These bits allow manual control of DAC2. Bit dacgpo_owen must be set to 1 to allow this mode of operation. These bits control DAC1. These bits set the transmitter synthesizer frequency in 50 kHz steps from 0 MHz to 3276.75 MHz. For the high bands, this is equal to the channel frequency, and for the low bands it is 2x the channel frequency. For example: Bit 15 to Bit 0 (Hex) HB Synthesizer Frequency LB synthesizer Frequency 0xA730 2140 MHz 1070 MHz 0xA988 2170 MHz 1085 MHz
[10:9]
test_Q/swap_Q
[8:7]
gain_blanksel
6 [5:0] 15: [14:11]
cmmod vcm_sat_thres dacgpo_owen gpo_ow
22, A1
[10:5] [4:0] [15:0]
padac2_ow padac1 txfreq
26, A1 Write
Rev. 0 | Page 27 of 36
ADF4602
Register 28, A1 Write Bit [15:4] Bit Name txpwr_set Description Requested transmit power at antenna. LSB = 1/32 dBm, 0x000 = -80 dBm, 0xFFF = 47.96875 dBm. The output power is referenced to a full scale sine wave applied to the transmit baseband inputs. For WCDMA modulated signals, the output power measured in a 3.84 MHz bandwidth is reduced by the peak to average ratio of the signal. See the I/Q Modulator section for more details. The valid range of transmit output power setting is -80 dBm to +10 dBm. Output clipping may occur sooner, depending on the PAR of the applied signal. The txpwr_set register should be updated periodically, or with every 5C change in temperature to ensure accurate output power. See the VCO Output section for more details. Set this bit to 1 to control the output power from the txpwr_set bits. Setting this bit to 1 triggers a manual load of the nonvolatile memory contents. See the Software Initialization Procedure section for more details.
31, A1 Write
1
0 4
nvmld
X = don't care.
Table 13. Sub-Address Registers
Register 0.144, A2 Write 0.151, A2 Write Bit [2:1] [7:0] Bit Name reserved[1:0] vsup2[7:0] Description These bits should be set to 11 for normal operation. These bits control the VSUP2 regulator voltage and should be set to 0x6F for normal operation. During the initialization sequence, the VSUP2 voltage is temporarily set to 3.1 V. See the Software Initialization Procedure section for more details. These bits should be set to 0x85 for normal operation. These bits should be set to 0x78 for normal operation. These bits should be set to 0x20 for normal operation. These bits enable the I, IB, Q, and QB channels of the modulator separately. Set these bits to all 1s to enable the modulator for normal operation. This bit controls the transmit VCO buffer state. For transmit synthesizer frequencies > 2100 MHz (Band 1) the buffer state should be set to 1, and the corresponding VCO buffer value in R0.174 should be set to 0x5F. This ensures correct device operation for frequencies > 2100 MHz. For operation below 2100 MHz (Band 2). the buffer state should be set to 0, and the corresponding VCO buffer value in R0.174 should be set to 0x50. This ensures correct device operation for frequencies < 2100 MHz. These bits should be set to 0x5F for transmit frequencies >2100 MHz, and 0x50 for transmit frequencies <2100 MHz. See the description for Register 0.171 for more. These bits should be set to 0x14 for normal operation.
0.153, A2 Write 0.155, A2 Write 0.165, A2 Write 0.170, A2 Write 0.171, A2 Write
[7:0] [7:0] [7:0] [7:4] 2
reserved[7:0] reserved[7:0] reserved[7:0] en_mix[3:0] buffstate
0.174, A2 Write 0.175, A2 Write
[7:0] [7:0]
buff_value[7:0] reserved[7:0]
Rev. 0 | Page 28 of 36
ADF4602 SOFTWARE INITIALIZATION PROCEDURE
INITIALIZATION SEQUENCE
Table 14 shows the initialization sequence that should be used after power-up. Note that the 26 MHz reference clock must be applied to the REFIN pin before programming begins. The default settings are described in the comments section, and some settings, such as output frequency, gain, and GPO settings, may vary from those required in the end application of the user. The user can substitute his own settings in these instances. Table 14. Initialization Sequence
Step 1 Register 1 02 Data 0x0003 Comment Performs a soft reset of the ADF4602. The reset takes 50 s, and no registers should be written to during this period. After 50 s, programming can continue as normal. This bit is self clearing. If using 1.8 V logic levels, this register should be programmed to 0x0001 instead of 0x0003. Set VSUP2 to 3.1 V. See the Nonvolatile Memory (NVM) Initialization section for more details. Transfers non-volatile memory (NVM) contents to registers. Wait 200 s before next programming step. Negate bit set in last programming step. Set VSUP2 back to 2.8 V. Enables receiver and disables transmit output. Selects TXHBRF pin as the transmit output and RXHB1 as the receive input. Enables all on-chip regulators. 19.2 MHz output clock is enabled, 26 MHz output clock is disabled. If it is desired to disable the 19.2 MHz output clock, this register is programmed to 0x27DD. Default settings for mixer and LNA gain reduction steps. Default settings. Default settings. Sets received gain calibration, WCDMA filter mode, and output common-mode voltage to 1.4 V. Default settings. Enables DAC and GPO manual control. Default settings. Default settings. Default settings. Default settings. Default settings. If transmit synthesizer frequency is >2100 MHz If transmit synthesizer frequency is <2100 MHz If transmit synthesizer frequency is >2100 MHz If transmit synthesizer frequency is <2100 MHz Default settings. Receiver gain set to 80 dB. Receiver synthesizer frequency set to 1950 MHz. The PLL takes 200 s to lock. Registers should not be written to during this period. Transmit synthesizer frequency set to 2140 MHz. The PLL takes 200 s to lock. Registers should not be written to during this period. Enables transmit output. Enables control of the output power and sets the txpwr_set field to 0 dBm. Control of output power is via the txpwr_set bits.
2 3 4 5 6
0.151 31 31 0.151 01
0xE0 0x0010 0x0000 0x6F 0x2FDD
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
1
12 13 14 15 21 22 0.144 0.155 0.153 0.165 0.170 0.171 0.174 0.175 11 10 26 01 28
0x0FA6 0x103E 0xEE53 0x0890 0x001F 0x8000 0x06 0x78 0x85 0x20 0xF0 0x04 0x00 0x5F 0x50 0x14 0x0050 0x9858 0xA730 0x2FFD 0xA001
Register numbers 0.xxx are 8-bit registers as described in the SPI Interface section of the ADF4602-x datasheet.
Rev. 0 | Page 29 of 36
ADF4602
Nonvolatile Memory (NVM) Initialization
The ADF4602 has on-chip non-volatile memory (NVM) that contains chip factory calibration coefficients. A soft reset of the device transfers the contents of NVM to internal registers; however, this has been found to be unreliable if performed at temperatures below 0C. The software work-around outlined in Step 2 to Step 5 of Table 14 ensures that the NVM data is transferred reliably under all operating conditions. It involves setting the VSUP2 on-chip regulator to 3.1 V, manually transferring the data by setting the nvmld bit in Register 31, and then resetting the VSUP2 regulator to 2.8 V. Device programming can then continue as normal. matically turned off to prevent any unwanted transmissions as the PLL locks. The user should wait 200 s (time taken for PLL to lock), and then set the output power to the desired value by writing to Register 28. If the user disables the transmit synthesizer, the transmit output power must be turned off before reenabling the transmit synthesizer. This is achieved by two means: setting Bit D5 in Register 1 or setting the output power in Register 28 to a minimum. After reenabling the synthesizer, and then locking the synthesizer to a frequency by programming the frequency word in Register 26, the user can reenable the output power. To change the receive frequency, simply program the new frequency in Register 10, and wait 200 s before using the device as a transceiver. The receive gain is set at any time (apart from during the 200 s PLL locking transient).
Programming Transmit and Receive frequencies
After initialization, the transmit/receive synthesizer frequencies may need to be changed. To change the transmit frequency, write the new frequency word to Register 26. When a new transmit frequency is programmed, the transmit output power is auto-
Rev. 0 | Page 30 of 36
ADF4602 APPLICATIONS INFORMATION
INTERFACING THE ADF4602 TO THE AD9863
The AD9863 mixed signal front-end processor is recommended for use with the ADF4602. The AD9863 contains dual 12-bit ADCs and dual 12-bit DACs for sampling the ADF4602 receive signal and providing the transmit baseband signal to the ADF4602. This section discusses the connections necessary between the devices.
is not optimum for the ADF4602. With the DAC gain set permanently at maximum, the transmit output power is controlled via the ADF4602 Tx power setting.
AD9863
IOUT+A DACA RDC IOUT-A TXBBIB TXBBQ RDC RDC TXBBQB RL Q INPUT
07092-044
ADF4602
TXBBI RDC RL I INPUT
Transmit Interface
The AD9863 TxDAC core provides dual, differential current output DACs generated from the 12-bit data. The full scale output current, IOUTFSMAX, is set by means of an external resistor, RSET. The relationship between IOUTFSMAX and RSET is as follows:
I OUTFSMAX
IOUT+B DACB IOUT-B
1.23 V = 67 x R SET

Figure 45. AD9863 TxDAC to ADF4602 Baseband Input Interface
Receive Interface
The AD9863 ADC input consists of a differential input resistance of 2 k and a switched capacitor circuit with a 2 V p-p differential full scale input level. The input is self biased to mid-supply, or, alternatively, is programmed to accept an external dc bias. The ADF4602 receive baseband outputs can provide this external dc bias (1.4 V), and this is the preferred interface between the two devices. The vcmsel bit in Register 15 should be set to 1 to give the 1.4 V common-mode voltage from the ADF4602, and the AD9863 input bias should be disabled. A direct connection can then be made between the ADF4602 receive baseband outputs and the AD9863 ADC inputs. The sampling action of the ADC sample and hold capacitor can introduce a kick-back effect onto the input signal. This can lead to spurs in the receive signal at integer multiples of the ADC sampling frequency. These spurs can degrade the sensitivity of the receiver on channels containing these spurs. To reduce these spurs and improve the sensitivity, filtering capacitors of 100 pF to ground should be placed on each receive baseband output. Figure 46 shows the interface between the two devices.
Setting RSET to 3.9 k gives the optimal dynamic setting for the TxDACs and results in a full scale output current of 20 mA. The ADF4602 transmit baseband inputs accept a 1.2 V commonmode input signal with 1 V p-p differential swing. The configuration in Figure 45 is used to provide this from the AD9863 TxDACs. Resistor RDC set up the dc common-mode voltage, whereas load Resistor RL sets the differential swing. The differential swing, VDIFF, is a function of the load resistor, RL, and the DAC full scale current, IOUTFSMAX, according to
VDIFF = 2 x I OUTFSMAX x R DC x R L 2 x R DC + R L = f (I OUTFSMAX ) = g (R L )
The common-mode voltage VCM is set by
VCM =
I OUTFSMAX x RDC 2
Using these equations, RDC is set to 120 to give 1.2 V commonmode voltage, and RL is set to 63 to give a 1 V p-p differential input swing. The AD9863 transmit programmable gain amplifier (TxPGA) provides 20 dB of simultaneous gain range for both DACs and is controlled via the SPI port. The gain is in the range of 10% to 100% IOUTFSMAX. Coarse gain controls are also available for each DAC output. Maximum settings (255) for both TxPGA gain and coarse gain controls (full gain) are recommended. This is because the DAC output common-mode voltage VCM is designed with a specific IOUTFSMAX. Varying the DAC gain results in a different IOUTFSMAX and consequently, a different VCM, which
Receive Sensitivity
Figure 26 shows the ADF4602 receive sensitivity vs.frequency. The sensitivity degradation due to the 63rd and 64th harmonics of the 30.72 MHz ADC sampling frequency can be seen near 1935 MHz and 1966 MHz. The 100 pF filtering capacitors to ground were used at the ADC inputs for this plot. Note also the sensitivity degradation due to the 26 MHz reference frequency harmonics at 1924 MHz, 1950 MHz, and 1976 MHz. The degradation in sensitivity is less than 3 dB for these harmonics. Overall, the solution exceeds the 3GPP sensitivity specifications by 6 dB across the frequency range.
Rev. 0 | Page 31 of 36
ADF4602
AD9863
IOUT+A ADCA IOUT-A C2 100pF IOUT+B ADCB IOUT-B C4 100pF RXBBQ C3 100pF RXBBQB QOUTPUT
07092-045
ADF4602
RXBBI C1 100pF RXBBIB I OUTPUT
Figure 46. ADF4602 Receive Baseband Output to AD9863 ADC Interface
Rev. 0| Page 32 of 36
ADF4602 OUTLINE DIMENSIONS
6.00 BSC SQ 0.60 MAX
31 30 40 1
0.60 MAX PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
5.75 BSC SQ
0.50 BSC 0.50 0.40 0.30
EXPOSED PAD
(BOT TOM VIEW)
4.25 4.10 SQ 3.95
10
21 20
11
0.25 MIN 4.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 47. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm x 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters
ORDERING GUIDE
Model1 ADF4602BCPZ ADF4602BCPZ-RL
1
Temperature Range 0C to +85C 0C to +85C
Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
072108-A
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
Package Option CP-40-1 CP-40-1
Z = RoHS Compliant Part.
Rev. 0 | Page 33 of 36
ADF4602 NOTES
Rev. 0 | Page 34 of 36
ADF4602 NOTES
Rev. 0 | Page 35 of 36
ADF4602 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07092-0-10/09(0)
Rev. 0 | Page 36 of 36

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